CAM modified to be used for statistic calculation in network switches and routers

ABSTRACT

A content addressable memory (CAM) device includes a plurality of entries each having an associated counter. When a CAM entry matches a search word stored in the comparand register of the CAM device, the matching entry&#39;s counter may be incremented. Alternatively, if there are multiple matching entries, in some instances only one matching entry has its counter incremented. The counter value can be written or read as part of either the least significant or most significant bits of the CAM entry.

FIELD OF INVENTION

[0001] The present invention relates generally to semiconductor memorydevices, and more particularly, a content addressable memory (CAM) beingused to process statistical data.

BACKGROUND OF THE INVENTION

[0002] An essential semiconductor device is semiconductor memory, suchas a random access memory (RAM) device. A RAM allows a memory circuit toexecute both read and write operations on its memory cells. Typicalexamples of RAM devices include dynamic random access memory (DRAM) andstatic random access memory (SRAM).

[0003] Another form of memory is the content addressable memory (CAM)device. A CAM is a memory device that accelerates any applicationrequiring fast searches of a database, list, or pattern. CAMs providebenefits over other memory search algorithms by simultaneously comparingthe desired information (i.e., data in the comparand register) againstthe entire list of pre-stored entries. CAM devices are frequentlyemployed in network equipment, and more specifically, in network routersor switches, where frequently at least a portion of a network addressmust be searched against a database in order to determine how to furtherroute a packet of data.

[0004] There are two types of searches which are of interest, namely asearch for the exact match and the partial match search. In the exactmatch search, an entry stored in the CAM will match the data sample onlyif the data sample and the entry match bit for bit. In a partial matchsearch, the search may be conducted on only a subset of bits in theword. That is, the CAM cells are permitted to specify a third “don'tcare” state in addition to the logical “0” and “1” states. When apartial match search is conducted, CAM cells will match a data sample aslong as each bit in the entry set at a logical “0” or “1” states matchthe corresponding portion of the data sample. CAMs which support onlyexact match circuits are generally known as binary CAMs, while CAMswhich also support partial match searches are generally known as ternaryCAMs.

[0005] In order to perform a memory search, CAMs are organizeddifferently than other memory devices (e.g., DRAM and SRAM). Forexample, data is stored in a RAM in a particular location, called anaddress. During a memory access, the user supplies an address and readsor gets data stored at the specified address. In a CAM, however, data isstored in locations in a somewhat random fashion. The locations can beselected by an address bus, or the data can be written into the firstempty memory location. Every location has a plurality of status bitsthat keep track of status information, for example, whether the locationis storing valid information.

[0006] Once information has been stored in the CAM entries (each entrycontaining a plurality of CAM cells), it can be found by writing asearch expression to a comparand register of the CAM. Each CAM entry isassociated with a local match detection circuit, which returns a “match”or “no match” indication based on a comparison between the content ofthe comparand register and the local CAM entry. If at least one localmatch detection circuit returns a “match” indication, the search issuccessful and the address of the CAM entry matching the searchexpression may also be output by the CAM. If multiple CAM cells return a“match” indication, the CAM may have a priority encoder and only outputthe address of the highest priority matching CAM entry. Thus, incontrast to conventional memory devices, in a CAM the user supplies thedata and gets back an address if there is at least one match found inthe CAM.

[0007] In many network devices, there is a need to gather statisticsrelating to the operation of the network device and/or the networktraffic processed by the device. For example, a router may compilestatistics relating to the amount of traffic processed over a givenperiod of time, perhaps organized or divided into subcategories (e.g.,by source and/or destination addresses, packet size distribution, timeof day, etc.) The router can be programmed with an expected baseline forthe statistics it gathers and the router could also alert a networkadministrator if the statistics gathered by the router deviate beyond apredetermined threshold from the norm. Such an ability may alert annetwork administrator to possible configuration errors, malfunctions, orattacks. Traditionally, network statistics are maintained usingdedicated circuits and/or software routines which gather and maintainnetwork statistics in reserved memory locations and/or registers. Theuse of dedicated circuits and/or software routines is not efficient andmay not be sufficiently flexible. Accordingly, there is a desire andneed for an efficient and flexible method and apparatus to gatherstatistics.

SUMMARY OF THE INVENTION

[0008] The present invention is directed to a content addressable memory(CAM) device which is adapted to function as the central component of astatistics gathering unit for a processing system. The processing systemis modified to present to the CAM for search, a series of status words,while the CAM has a number of cells programmed to match status wordssignifying events of statistical interest. The CAM is modified so thateach CAM entry is associated with a counter, which can be read, written,incremented, or reset. Additionally, the CAM includes at least oneprocessing unit, which can be used to perform mathematical operationupon CAM values. Generally, whenever a CAM entry matches a status word,the counter associated with each matching CAM entry is incremented.However, in some embodiments, if multiple CAM entries match a statusword, only the highest priority entry increments its counter. In otherembodiments, instead of The statistic can be obtained by reading thecounter value portion of the CAM cell.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The foregoing and other advantages and features of the inventionwill become more apparent from the detailed description of exemplaryembodiments of the invention given below with reference to theaccompanying drawings, in which:

[0010]FIG. 1 is a block diagram of a CAM memory device implementing theinvention;

[0011]FIG. 2 is a block diagram of processor based system utilizing theCAM memory device of the present invention; and

[0012]FIGS. 3A, 3B, and 3C are exemplary diagrams of a status word andCAM entries for ternary and binary CAMs, respectively.

DETAILED DESCRIPTION OF THE INVENTION

[0013] Now referring to the drawings, where like reference numeralsdesignate like elements, there is shown in FIG. 1 a CAM device 100. TheCAM device 100 is preferably a ternary CAM device, although the presentinvention may also be practiced using a binary CAM device. The CAMdevice 100 includes a read register 110 for buffering data to be readout of the CAM device 100 on line 111. The read register 120 is coupledto the comparand register 120 and a plurality of CAM entries 130 usinglines 141-142. Although not illustrated in FIG. 1, some CAM devices mayalso include a write register. A write register is a register similar tothe read register 110, but used to buffer write data instead of readdata. Further, while FIG. 1 illustrates a single set of lines 141-142,some CAM devices may use multiple sets of lines. For example, a firstset of lines may couple the comparand register to each CAM entry while asecond set of lines may couple the read/write register(s) to each CAMentry.

[0014] The plurality of CAM entries 130 each comprise a first datastorage portion DATA 131 for holding data, and a second data storageportion COUNTER 132 for holding a counter value. The COUNTER 132 can beincremented by setting the INC line 135 to a predetermined state. (Itshould be noted other embodiments may include counters which aredecremented instead of being incremented, or counters which can beincremented or decremented.) Both the DATA 131 and COUNTER 132 portionsare coupled via lines 141, 142, respectively, to the read register 110,so that both portions may be read out of the CAM device. Each CAM entry130 additionally includes a match detector circuit 133. The matchdetector circuit 130 asserts a MATCH signal on line 134 if the DATA 131and COUNTER 132 content match the search expression stored in comparand120.

[0015] The MATCH signal is supplied via line 134 to the priorityindicator 150, which may assert the increment signal INC on each line135 which corresponds to a matching CAM entry, or on only the line 135which corresponds to the highest priority matching entry. The behaviorof the priority indicator 150 can be switched between these two modes bychanging the logical state of the line 151 attached to the ENABLEterminal of the priority encoder. The priority encoder is furthercoupled via lines 152 to an address encoder 160, and outputs thematching addresses having the highest priority on line 161.

[0016] The CAM device 100 further includes a processor 170, which iscoupled to both the data line 180, used to supply data to the CAM device100, as well as lines 142 used to carry the content of the countervalues. The processor 170 outputs the result of its processing on line171. The processor 170 can therefore be used to perform mathematicaloperations on counter values. At a minimum, the processor 170 mustinclude an adder, so that counter values can be added or subtracted.However, the processor 170 may also be much more sophisticated than anadder, and may be, for example, a multi-function mathematics processor,or a microprocessor. In general, the processor 170 may be used tofurther post process the counter values in order to facilitate thecomputation of statistical information.

[0017]FIG. 2 is an illustration of a processor based system 200 designedfor use with the CAM device 100 of FIG. 1. As illustrated, the system200 is a network router, however, the system 200 may be any type ofsystem which may benefit from the statistic support which can beprovided by the CAM device 100. The router 200 includes a centralprocessor (CPU) 210 coupled to a bus 240. Also coupled to the bus 240 isthe CAM device 100 of FIG. 1, a random access memory (RAM) 220, aconventional CAM device 221, a read only memory (ROM) 222, and aplurality of network interfaces 230.

[0018] The router 200 operates by having the CPU 210 execute a boot-uproutine stored in the ROM 222, which causes the router 220 to acceptconfiguration data from one of the network interfaces 230. Theconfiguration data is used to set up routing information, which may bestored in the RAM 220. Addition information may also be stored in theconventional CAM 221. Once configured, the router 200 accepts networkpackets from at least one of the network interfaces 230, analyzescertain fields of each accept packet, including, for example, source anddestination addresses. The CPU 210, with the help of the information inRAM 220 and conventional CAM device 221, determines whether to forwardthe packet from one of the plurality of network interfaces 230 toanother one of the plurality of network interfaces.

[0019] In order to utilize the statistical support feature of the CAMdevice 100 of FIG. 1, the relevant parameters which define the operationof a system 200 must be identified. For example, one statistic which maybe helpful for capacity planning may include the identification of thenumber of packets forwarded to or received from a particular network, ornetwork node. In order to perform this analysis, the source anddestination addresses of each packet must be analyzed. Thus, sourceaddress and destination address fields will be relevant parameters forthe router 200. Similarly, since packets can vary in size, it may beuseful to develop an understanding of the distribution of packet sizesfor the packets processed by the router 200. In order to perform thisanalysis, its clear that the packet size field must be analyzed. Thus,the packet size field of a packet will be a relevant parameter for therouter 200. In some instances, combinations between different statisticsmay also be helpful. For example, packet size distribution may varybetween different networks. Thus, source address, destination address,and packet size are relevant parameters if statistics relating to packetsize distribution by network is required.

[0020] Once the relevant parameters have been identified, the CPU 210(or another processing element) of the system 200 can be programmed topresent as a search word to the CAM 100 of FIG. 1, a status word havingfields corresponding to the relevant parameters. In the above discussedexample, the relevant fields are each packet's source address,destination address, and packet size. If the addresses are, for example,TCP/IP addresses, the source and destination addresses would each be32-bit addresses. The packet size might be a 16-bit field. Referring nowto FIG. 3A, an example of a status word 301 which could be generatedwould be a 80-bit field comprising a 32-bit source address, a 32-bitdestination address, and a 16-bit packet length field which specifies inbytes, the size of the packet.

[0021] The CPU 210 of the router 200 would also write certain entries ofthe CAM 100, in the same format of the status word, to correspond to thestatistics to be gathered. For example, if one statistic we wanted togather is the number of packets processed by the router which originatedin a network having TCP/IP addresses ranging from 192.168.0.0 to192.168.0.255, one CAM entry 302 (FIG. 3B) in CAM 100 may have its dataportion encoded as (hexadecimal) “C0A8 00XX XXXX XXXX XX,” where C0hexadecimal equals 192 decimal, A8 hexadecimal equals 168 decimal, 00hexadecimal equals 0 decimal, and XX corresponds to “don't care.” If weadditionally wanted to know how many packets were originating from theTCP/IP address range of 192.168.0.0 to 192.168.0.255 and heading to aTCP/IP address in the range of 10.0.0.0 to 10.0.255.255, the CPU 210would construct another CAM entry 303 encoded as (hexadecimal) “C0A800XX 1000 XXXX XX,” where 10 hexadecimal equals 10 decimal. The CPU 210of the router would also reset the COUNTER 132 portion of both CAMentries to zero. Similarly, to count the number of packets processed bythe router 200 have a packet length between 16 to 31 bytes, the CPU 210would construct a CAM entry 304 encoded as (hexadecimal) “XXXX XXXX XXXXXXXX 1X.”

[0022] During normal operation of the router, the CPU 210 will constructa status word for each packet processed, and present that status word asa search term in the comparand register 120 of the CAM device 100. Thefirst CAM entry 302 will match any packet having an originating TCP/IPaddress in the range of 192.168.0.0-192.168.0.255 regardless ofdestination while the second CAM entry 303 will match any packet havingthe specified originating address and having a destination addressbetween 10.0.0.0-10.0.255.255. The third CAM entry 304 will match anystatus word indicating a packet having a length between 16 and 31 bytes,regardless of source or destination address. In order to properly counteach statistic, line 151 (FIG. 1) should be set to a logical state whichcause the priority indicator circuit 150 to cause every matching CAMentry to increment its counter. At any given time, the statistics can beaccessed by reading the three CAM entries 302-304 and extracting theirrespective counter value fields.

[0023] Note that the CAM 100 is preferably a ternary CAM, so that it maystore entries having “don't care” states. This is advantageous becauseit permits one CAM entry to match a wide range of status words. However,the CAM 100 may also be a binary CAM, albeit at an expense of using moreCAM entries and being more limited. For example, assume that therelevant parameters for the router 200 is only the originating TCP/IPaddress and thus the status word is 32-bit wide instead of 80-bit wide.In order to compile statistics regarding the number of packetsoriginating from the network having TCP/IP addresses of 192.168.0.0 to192.168.0.255, a binary CAM would require the CPU 210 to write 256 CAMentries 310, 311, 312, namely (hexadecimal) C0A8 0000, C0A8 0001, . . ., C0A800FF. In order to extract the statistics, the counter values ofthe 256 CAM entries will need to be summed using, for example, processor170.

[0024] The present invention therefore provides for a CAM architecturewhich integrates a counter into the CAM cell. The counter can bechanged, i.e., incremented and/or decremented, using a signal, which iscoupled to a priority indicator circuit 150. Additionally, the countercan be read or written as it is also a sequence of bits in each CAMentry. A system which requires statistics support can utilize the CAM ofthe present invention to flexibly and quickly gather statistical data byprogramming the entries of the CAM to correspond to the desiredstatistics and presenting to the CAM a status word for search for eachprocessing activity. A processor in the CAM can further facilitate thecomputation of statistical data by performing mathematical operationsupon counter values.

[0025] While the invention has been described in detail in connectionwith the exemplary embodiment, it should be understood that theinvention is not limited to the above disclosed embodiment. Rather, theinvention can be modified to incorporate any number of variations,alternations, substitutions, or equivalent arrangements not heretoforedescribed, but which are commensurate with the spirit and scope of theinvention. Accordingly, the invention is not limited by the foregoingdescription or drawings, but is only limited by the scope of theappended claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A method of operating a content addressablememory (CAM) comprising: accepting a search word; simultaneouslysearching a plurality of CAM entries to identify at least one matchingCAM entry; and changing a counter portion of at least one of said atleast one matching CAM entry.
 2. The method of claim 1, wherein saidchanging is incrementing.
 3. The method of claim 1, wherein saidchanging is decrementing.
 4. The method of claim 1, further comprising,outputting an address corresponding to one of said at least one matchingCAM entry.
 5. The method of claim 1, wherein in said step of changing,the counter portion of each of said at least one matching CAM entry isincremented.
 6. The method of claim 1, wherein in said step of changing,the counter portion of one of the at least one matching CAM entry isincremented.
 7. The method of claim 6, wherein which one of said atleast one matching CAM entry is incremented is based on a priority ofsaid at least one matching CAM entry.
 8. The method of claim 7, whereinwhich one of said at least one matching CAM entry is incremented isbased on a highest priority of said at least one matching CAM entry. 9.The method of claim 1, further comprising: performing an mathematicaloperation using the counter portion of one of said matching CAM entry.10. The method of claim 4, wherein said mathematical operation isaddition.
 11. The method of claim 1, further comprising: reading a CAMentry; wherein said CAM entry includes a data portion of said CAM entryand a counter portion of said CAM entry.
 12. The method of claim 1,further comprising: writing a CAM entry; wherein said CAM entry includesa data portion of said CAM entry and a counter portion of said CAMentry.
 13. The method of claim 1, wherein said step of simultaneouslysearching searches binary CAM entries.
 14. The method of claim 1,wherein said step of simultaneously searching searches ternary CAMentries.
 15. A content addressable memory (CAM) device, comprising: acomparand register for storing a search expression; a read register; aplurality of CAM entries, said plurality of CAM entries coupled to saidcomparand register and said read register, each comprising, a datastorage portion; a counter portion; and a match detection circuit foroutputting a match signal if said data storage portion and counterportion corresponds to said search expression.
 16. The device of claim15, further comprising, a priority indicator, coupled to said pluralityof CAM entries, for receiving match signals outputted by said matchdetection circuits, and for changing a counter portion of at least oneof said plurality of CAM entries which outputted the match signal. 17.The device of claim 16, wherein said changing includes incrementing thecounter portion.
 18. The device of claim 16, wherein said changingincludes decrementing the counter portion.
 19. The device of claim 16,further comprising, an address encoder, coupled to the priority encoder,for outputting an address corresponding to one of said plurality of CAMentries which outputted the match signal.
 20. The device of claim 15,wherein said priority indicator increments the counter portion of everyone of said plurality of CAM entries which outputted the match signal.21. The device of claim 15, wherein said priority indicator incrementsthe counter portion of only one of said plurality of CAM entries whichoutputted the match signal.
 22. The device of claim 15, furthercomprising: a mathematical processor, coupled to the counter portion ofthe plurality of CAM entries, for performing a mathematical operationusing at least one of said counter portions.
 23. The device of claim 22,wherein said mathematical operation is addition.
 24. The device of claim22, wherein said mathematical processor is a multi-function processor.25. A system, comprising: a processor; a content addressable memory(CAM), coupled to said processor, said content addressable memory (CAM)device further comprising, a comparand register for storing a searchexpression; a read register; a plurality of CAM entries, said pluralityof CAM entries coupled to said comparand register and said readregister, each comprising, a data storage portion; a counter portion;and a match detection circuit for outputting a match signal if said datastorage portion and counter portion corresponds to said searchexpression.
 26. The system of claim 25, further comprising, a priorityindicator, coupled to said plurality of CAM entries, for receiving matchsignals outputted by said match detection circuits, and for changing acounter portion of at least one of said plurality of CAM entries whichoutputted the match signal.
 27. The system of claim 26, wherein saidchanging includes incrementing the counter portion.
 28. The system ofclaim 26, wherein said changing includes decrementing the counterportion.
 29. The system of claim 26, further comprising, an addressencoder, coupled to the priority encoder, for outputting an addresscorresponding to one of said plurality of CAM entries which outputtedthe match signal.
 30. The system of claim 25, wherein said priorityindicator increments the counter portion of every one of said pluralityof CAM entries which outputted the match signal.
 31. The system of claim25, wherein said priority indicator increments the counter portion ofonly one of said plurality of CAM entries which outputted the matchsignal.
 32. The system of claim 25, further comprising: a mathematicalprocessor, coupled to the counter portion of the plurality of CAMentries, for performing a mathematical operation using at least one ofsaid counter portions.
 33. The system of claim 32, wherein saidmathematical operation is addition.
 34. The system of claim 32, whereinsaid mathematical processor is a multi-function processor.